UNIT_2: Instruction set of 8086
Data Transfer Instructions-8086
R20 MPMC UNIT-1:: Instruction set of 8086 microprocessor -PDF
AY:2022-23, SEM-II
UNIT-2: INSTRUCTION SET OF 8086 MICROPROCESSOR- PDF
Instuctionset of 8086 & Instuction format -PDF
The instruction set of 8086 can be classified into
1. Data Transfer Instructions
2. Arithmetic Instructions
3. Logical Instructions
4. String Manipulating Instructions
5. Control transfer Instructions
6. Processor control instructions
The size of 8086 instruction is one to six bytes.
In general the first byte of instruction will have a 6-bit opcode
and two special bit indicators d-bit and w-bit (or s-bit and w-bit )
(or v-bit and w-bit)
Some instructions will have 7-bit opcode and one special bit
indicator w-bit or z-bit
Some instructions will have 8-bit opcode
Some of the instructions will have 3-bit register field in the first
byte of the instruction
R20 MPMC UNIT-1:: Interrupts of 8086 -Notes
AY:2022-23, SEM-II
UNIT-1: Interrupts of 8086- Interrupt Response
The interrupts of 8086 are :
1. Hardware Interrupts
2. Software Interrupts
3. Divide -by - Zero Interrupt (Type -0 Interrupt)
4. Single Step (or) TRAP Interrupt (Type -1 Interrupt)
5. Non-Maskable Interrupt (NMI) (Type-2 Interrupt )
6. Break-point Interrupt (Type -3 Interrupt)
7. Overflow Interrupt (Type -4 Interrupt)
R20 MPMC UNIT-1:: 8086 Logic pin out - Signal description -Notes
AY: 2022-23, SEM-II
UNIT-1:: 8086 Logic pin out - Signal description -Notes
INTEL 8086 IC has the following limitations
1. 8086 has multiplexed address, data and status signals
therefore these signal lines are to be Demultiplexed
2. Appropriate control signals need to be generated for
interfacing memory and I/O devices to 8086 processor
R20 MPMC UNIT-1:: 8086 Architecture - BIU - EU
AY:2022-23 sem-II
UNIT-1: Architecture of 8086
Bus Interfacing Unit (BIU) : Functional units of BIU
Segment registers, Instruction Pointer, Address Generation Unit , Instruction Queue, Bus control logic
Executing Unit (BU): Functional units of EU
General purpose registers (GPRs), Pointer and Index registers , ALU , Flag register
UNIT –V
DigitalToAnalogAndAnalogToDigitalConverters:Introduction,basicDACtechniques,weighted
resistor DAC,R-2RladderDAC,invertedR-2RDAC,A-DConverters– parallel Comparator type
ADC, counter type ADC, successive approximation ADC and dual slope ADC.DAC and ADC
Specifications.
UNIT –IV
Timers: Introduction to 555 timer, functional diagram, Monostable and Astable operations and
applications, Schmitt Trigger.
Phase Locked Loops: Introduction, block schematic, principles and description of individual
blocks, 565 PLL, Applications of PLL – frequency multiplication, frequency translation, AM,
FM & FSK demodulators. Applications of VCO (566)
UNIT-4 : IC 565 PLL APPLICATIONS
UNIT-4 : IC 555 Astable Multivibratior Applications
UNIT – III
Active Filters: Design & Analysis of Butterworth active filters – 1 st order, 2 nd order LPF, HPF
filters. Band pass, Band reject and all pass filters.
UNIT –II
OP-AMPS Applications: Introduction, Basic Op-Amp Applications, Instrumentation Amplifier,
AC Amplifier, V to I and I to V Converter, Sample and Hold Circuit, Log and Antilog Amplifier, Multiplier and Divider, Differentiator,integrator.
Comparators and Waveform Generators: Introduction, Comparator, Square Wave Generator,
Monostable Multivibrator, Triangular Wave Generator, Sine Wave Generators.
UNIT-2 : OPAMP Applications - Log and Antilog Amplifiers using op-amp
UNIT–I
OP-Amp Block Diagram (Symbolic Representation), Characteristics of Op-Amp, Ideal and
Practical Op-Amp specifications, DC and AC Characteristics, Definitions of Input and Output
Off-set voltage and currents slow rate, CMRR, PSRR. Measurements of Op-Amp Parameters,
UNIT_2: Instruction set of 8086 Data Transfer Instructions-8086 Instruction set -8086 summary